1. Field of the Invention
The present invention relates to an overdriving control circuit for accelerating the operation of a sense amplifier by setting an overdriving zone, and more particularly, to an improved overdriving control circuit capable of setting an optimized overdriving zone by sensing the potential of a bit line.
2. Description of the Background Art
In general, when a sense amplifier is activated according to a over-driven sense amplifier scheme, an external voltage VDD (for example, 3.3V) is initially supplied to improve a data sensing speed of the sense amplifier, and then a low-adjusted internal array voltage VDL (for example, 2.2V) is provided to maintain the accumulated voltage. Here, an overdriving zone denotes a time period during which the low-adjusted internal array voltage VDL is supplied following the provision of external voltage VDD.
As shown in FIG. 1, the conventional overdriving control circuit includes a delay unit 1 for delaying a sense amplifier enable signal SAEN, and a logic circuit unit 2 for logically combining the sense amplifier enable signal SAEN and the delayed sense amplifier enable signal and outputting an NMOS sense amplifier drive signal NSAD, a PMOS sense amplifier drive signal PSAD and a PMOS sense amplifier overdrive signal PSAOD.
The operation of the conventional overdriving control circuit will now be described with reference to the accompanying drawings.
First, the delay unit 1 receives sense amplifier enable signal SAEN as illustrated in FIG. 2A, and outputs an overdriving control signal ODED as a delayed sense amplifier enable signal. The logic circuit unit 2 receives the sense amplifier enable signal SAEN and overdriving control signal ODED to generate PMOS sense amplifier overdrive signal PSAOD having a pulse width equivalent to its delayed time as shown in FIG. 2C.
The PMOS sense amplifier overdrive signal PSAOD and NMOS sense amplifier drive signal NSAD of FIG. 2B are logically combined in the logic circuit unit 2 to produce PMOS sense amplifier drive signal PSAD as shown in FIG. 2D.
That is, in accordance with the PMOS sense amplifier overdrive signal PSAOD, an internal voltage VDL is provided in due time into the logic circuit unit 2 after the provision of external voltage VDD. In other words, the pulse width of PMOS sense amplifier overdrive signal PSAOD is determined as a fixed value by the delay rate of the delay unit 1.
As a result, when the overdriving region is determined by a predetermined delay rate and when there occurs a variation of the external voltage VDD or a bouncing of a source voltage, it becomes difficult to obtain a sufficient overdriving region.
Further, although the overdriving region is elongated in order to overcome such difficulty, there occurs an excessive current flow, thereby increasing power consumption.